1. Field of the Invention
This invention relates to a semiconductor substrate and a process for its production. More particularly, it relates to a semiconductor substrate comprising a silicon substrate and a single-crystal compound semiconductor form d thereon, suited for the fabrication of electronic d ices and formation of integrated circuits, and to process for its production. It also relates to an electronic device fabricated on this semiconductor substrate.
2. Related Background Art
Group IV elements belonging to Group IV of the periodic table, such as Si ad Ge, have been used from the beginning as materials for substrates (wafers) for semiconductor devices and have highly advanced. At present too, as well known, variety of electronic devices such as DRAMs, MPUs, logic ICs and analog ICs are fabricated on silicon (Si) substrates, and these elements are utilized as mat rials for active regions of diodes, MOS transistors a d bipolar transistors. These Group IV elements, however, are not suited for constituents of light-emitting diodes.
Meanwhile, Group III-V or II-VI compound semiconductors as typified by GaAs, GaP, InP, GaN and ZnSe are very suited for light-emitting devices such as LEDs and lasers. Research has been conducted thereon in great variety, and LEDs and semiconductor lasers have already been put into practical use. Also, HEMTs (High Electron Mobility Transistors) are prepared using these compound semiconductors, and high-frequency circuits that can be used at GHz band regions have been put into practical use.
Compound semiconductor substrates, however, have so low a mechanical strength that it is difficult to produce large-area wafers of compound semiconductors. Accordingly, such wafers have a fairly smaller size than silicon wafers, and hence are obtained at a lower production efficiency than silicon wafer processes. Moreover, the production cost of the wafer themselves is a little more than 10 times that of silicon wafers having the same size.
To overcome such problems, it has been attempted to promote heteroepitaxial growth of compound semiconductors on the silicon substrates that have a high mechanical strength and enable production of large-area wafers, as typified by GaAs on Si. This technique is a method by which light-emitting devices or high-speed electronic devices such as LEDs and lasers making use of compound semiconductors are formed on silicon substrates having a high mechanical strength and also being inexpensive and still also having a high thermal conductivity, thereby aiming at improvement of productivity, achievement of cost reduction and so forth and spread of these devices. In addition, since such light-emitting devices and high-speed electronic devices can be integrated on the same substrates as those of highly advanced Si-LSIs, it becomes possible to realize Opto-Eletronic Integrated Circuits (OEICs).
However, some problems are pointed out in respect of the growth of compound semiconductors on such Si, and there are many difficulties in the fabrication of devices by the use of the compound semiconductors grown on Si.
One of them is the occurrence of antiphase domains caused by polarity/non-polarity, which causes a great stress or lattice imperfections in epitaxial layers. The other is the presence of a difference in coefficient of thermal expansion and a lattice mismatch, which causes a stress or lattice imperfections between silicon substrates and compound semiconductor films.
The former can be restrained by using silicon substrates having off-angles. The latter can not be settled with ease, and many research institutes have made studies on various crystal growth techniques, but, at present, can not still break the barrier of 10.sup.6 /cm.sup.2 with ease in respect of the dislocation density that can be an indication of crystal quality. This is said to be due to a lattice strain caused by disagreement in lattice constant between silicon substrates and compound semiconductor layers. Lattice defects brought in at a high density may deteriorate device characteristics such as light-emitting characteristics and durability, and are not practical. Accordingly, it is sought to form on silicon substrates, III-V or II-VI compound semiconductor thin films having a low defect density comparable to compound wafers.
Many studies on single-crystal semiconductor films of IV--IV compounds such as SiC and SiGe are also reported as light-emitting materials, and these single-crystal compound-semiconductor films are also desired to be formed on silicon substrates. Thus, for similar reasons, it has been strongly demanded to decrease such crystal defects also when the single-crystal films of SiGe or SiC IV--IV compound type ones are formed on silicon substrates.
As discussed above in detail, the demand for heteroepitaxy by which single crystals having a good crystal quality are grown on silicon substrates is at a high level, but there is still only a low possibility of accomplishing it.
Many reports are made on heteroepitaxial growth on such silicon substrates.
Some reports have presented an attempt to form a porous silicon layer on the surface of a silicon substrate and make heteroepitaxial growth on that layer so as to decrease the crystal defects.
Ohmachi et al. have reported in The Society of Applied Physics 1987 20aX5, "GaAs Growth on Porous Si", NTT ECL Y. Ohmachi, W. Watanabe, Y. Kadota and H. Okamoto, that there are differences in surface properties and half width between an offset substrate and a just substrate when crystals are grown by MOCVD (Metal Organic Chemical-Vapor Deposition) and MBE (Molecular-Beam Epitaxy) on 10 .mu.m thick porous silicon substrates.
It is also known that, when GaAs crystals are grown by MBE on 10 .mu.m thick porous silicon substrates, their cross-sectional TEM observation reveals the presence of more defects than GaAs crystals grown on silicon substrates under the same conditions.
Thus, some attempts to improve crystal quality by the use of porous silicon are reported. Although the crystal strain of compound semiconductor layers formed by heteroepitaxial growth can be relieved in some instances, the compound semiconductors have so poor a crystal quality that it has been very difficult to apply them to devices.
In heteroepitaxial growth on silicon substrates having a main plane of (100)-plane in plane direction, the films grown commonly have rough surfaces. To solve this problem, it has been necessary to use what is called an offset substrate, in which the plane direction is angled by some degrees from the (110)-plane. The PA of FIG. 3 shows an off-angle dependence of surface roughness (average square roughness). In order to attain good surface morphology, the off-angle must be precisely controlled. Such precise control has tended to bring about an increase in yield and in substrate cost as well.
Meanwhile, in homoepitaxy on porous silicon substrates, the present inventors have discovered that, in silicon homoepitaxial growth by heat CVD using a source gas diluted with hydrogen, the crystal quality can be improved when surface pores are stopped up by hydrogen prebaking carried out immediately before the source gas is supplied (N. Sato, K. Sakaguchi, K. Yamagata, Y. Fujiyama and T. Yonehara, J. Electrochem. Soc. 142 (1995), p.3116).
FIGS. 2A and 2B are diagrammatic illustrations to describe a process in conventional techniques. In FIGS. 2A and 2B, reference numeral 20 denotes a porous layer (porous silicon substrate); 21, walls of the porous layer; 22, pores of the porous layer; 24, a single-crystal compound-semiconductor film; and 25, crystal defects.
First, a porous silicon substrate 20 is prepared (FIG. 2A). Next, the porous silicon substrate 20 is placed in a reaction chamber of a CVD apparatus, and a single-crystal film 24 of a compound semiconductor such as GaAs is formed by heteroepitaxial growth on the porous silicon substrate, using trimethyl gallium (TMGa) or arsine (AsH.sub.3) as a source gas (FIG. 2B).
In the single-crystal compound semiconductor film 24 thus formed, crystal defects 25 due to strain, lattice mismatch and grain boundaries are produced on the side of the surface 26 of the porous silicon substrate 20.